Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in circuit density produce a corresponding increase in overall chip packaging strategies in order to remain competitive. Chip and chip carrier manufacturers are therefore constantly being challenged to improve the quality of their products by identifying and eliminating problems, reducing package size and weight, decreasing package costs, providing improved thermal efficiencies and by producing better and more advanced chips. Whereas significant improvements are being made to eliminate systematic problems by reducing process variability. Process improvements alone are not sufficient to eliminate all the problems which effect both performance and reliability.
One way to increase performance and reliability is to provide the shortest and most efficient thermal cooling path for the integrated circuit chips. This could be done by bringing the chip physically as close as possible to the heat sink. Another way would be to provide more efficient cooling of the chip. However, when the chips are brought closer to the heat sink, means also have to be provided to securely provide a thermal contact between the chip and the heat sink. In some cases highly thermally conductive epoxies have been used to provide a better thermal contact between the chip and the heat sink. However, this would create a problem if different types of chips are present on the MCM, because some chips may be "under cooled" while others may be "over cooled".
The introduction of MCMs has helped packages perform better electrically, but at the same time it has made them more difficult to cool. Moving chips from single chip modules (SCMs) to MCMs greatly affects the module heat flux density, even when chip flux densities are unchanged. The cooling of large MCMs has been the subject of many inventions, such as, for example, the use of pistons to cool the chips, and most recently FPC (flat plate cooling). While the previous approaches used tight tolerance mechanisms to provide a thermal/mechanical path for the heat to flow from the chip to the cooling fluid (air or water).
Flat plate cooling uses much fewer parts, and it uses a single thermal compound to provide the cooling path between the chip and the flat plate. In general, the concept of FPC is to install a flat thermally conductive "hat" just above, and parallel to the chip back side surfaces. The gap between the chips and the hat is typically filled with a single thermally conductive material. The single thermally conductive material (thermal compound, grease or paste) is installed in specific locations with sufficient quantity so that the back side of each chip is entirely covered. Although the compliant thermally conductive material has a thermal conductivity much lower than the metals used in previous inventions, it is able to provide better thermal performance at a lower cost because the thickness of the paste filled gap is small, there are fewer interfaces for the heat to cross, and it is insensitive to chip pitch.
A typical application of FPC would be to have an array of chips on a substrate, where each had the same size and height, cooled by FPC. In this application, each chip would have the same thermal resistance to the cooling hat.
One example of flat plate cooling is Umezawa, et al., U.S. Pat. No. 5,023,695, where a heat conducting compound is present between the chips and the flat cooling plate.
Research Disclosure, No. 270, Publication No. 27014 (October 1986), the disclosure of which is incorporated herein by reference, discloses a stick-on heat sink. A heat sink is attached to a module by sliding the module into the heat sink and where the edges of the heat sink snap close to secure the heat sink to the module. It is also disclosed that an adhesive or double sided tape could also be placed on the bottom surface of the heat sink to assure intimate contact between the module and the heat sink.
U.S. Pat. No. 4,092,697 (Spaight), the disclosure of which is incorporated herein by reference, discloses placing a film of thermally conductive material between the chip and the heat sink or heat radiator.
U.S. Pat. No. 4,233,645 (Balderes et al.), discloses placing a block of porous material which is impregnated with a suitable liquid between the chip and the heat sink to provide a thermally conductive path.
U.S. Pat. No. 4,849,856 (Funari et al.), the disclosure of which is incorporated herein by reference, discloses a direct chip to heat sink attachment process where a thermally conductive adhesive is used to directly secure the heat sink to the chip.
U.S. Pat. No. 4,939,570 (Bickford et al.), the disclosure of which is incorporated herein by reference, discloses another direct chip to heat sink attachment process where a thermally conductive adhesive is used to directly secure the heat sink to the chip.
U.S. Pat. No. 4,999,699 (Christie, et al.), the disclosure of which is incorporated herein by reference, discloses solder interconnection whereby the gap created by solder connections between a carrier substrate and semiconductor device is filled with a composition obtained from curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof; filler having a maximum particle size of 31 microns and being at least substantially free of alpha particle emissions.
U.S. Pat. No. 5,249,101 (Frey, et al.), the disclosure of which is incorporated herein by reference, discloses a coverless chip carrier which uses at least two encapsulants. The first encapsulant is used to provide flip-chip fatigue life enhancement. The second encapsulant is used to provide limited environmental protection. A third encapsulant is also required for carriers using peripheral leads to contain the second encapsulant prior to curing. Also disclosed is that the encapsulant have a CTE (Coefficient of Thermal Expansion) which is within 30 percent of the CTE of the solder balls.
U.S. Pat. No. 5,325,265 (Turlik, et al.) discloses that cushions could provide a thermally conductive path between an exposed back face of a chip and a heat sink. Also disclosed is the fact that a solder preform may be used for the cushions with the preforms being held in place using grooves or cavities or a combination thereof.
The inventors of this invention, however, are using an entirely different approach to solve this age old problem. They are customizing the thermal cooling area by providing a different thermal coefficient thermal fluid or paste or compound for each chip so that each chip could be cooled within its specific specifications. Also disclosed is that by varying the depth of the gap or the blind hole which is filled with the individualized thermal fluid one could also further fine tune the individual cooling regimes.
Furthermore, the structure and process of this invention offers several advantages over the prior art. For example, it provides a customized thermal path with a simplified modular construction which allows the ease of workability or repair of the assembled module.